1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming a FinFET semiconductor device using a novel etching process to form the fins for the device wherein the etch rate of the etching process is modified by inclusion of dopant materials.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. For example, for an NMOS device, if there is no voltage applied to the gate electrode, then there is no current flow through the NMOS device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate positive voltage is applied to the gate electrode, the channel region of the NMOS device becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, there are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure. More specifically, in a FinFET, a generally vertically positioned fin-shaped active area is formed and a gate electrode encloses both sides and an upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects. When an appropriate voltage is applied to the gate electrode of a FinFET device, the surfaces (and the inner portion near the surface) of the fins, i.e., the substantially vertically oriented sidewalls and the top upper surface of the fin with inversion carriers, contributes to current conduction. In a FinFET device, the “channel-width” is approximately two times (2×) the vertical fin-height plus the width of the top surface of the fin, i.e., the fin width. Multiple fins can be formed in the same foot-print as that of a planar transistor device. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly stronger drive current than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond. A further improvement upon FinFET devices involves the use of a dielectric isolation material to completely isolate the “fin” channel from one another and the substrate. The isolation material tends to reduce leakage between neighboring FinFET devices as well as decrease leakage current between the source and drain that travels through the substrate in a typical “bulk” FinFET device.
FIGS. 1A-1F depict one illustrative prior art process flow for forming an illustrative FinFET semiconductor device 10 above a semiconductor substrate 12 comprised of, for example, silicon. FIG. 1A depicts the device 10 at a point of fabrication where an illustrative layer of silicon/germanium 14, a layer of silicon 16 and a patterned mask layer 18 have been formed for the device 10. The layer of silicon/germanium 14 and the layer of silicon 16 may be formed by performing known epitaxial growth processes. The masking layer 18 may be comprised of any of a variety of different materials, e.g., silicon nitride, and may be formed by depositing the layer(s) of material that comprise the masking layer 18 and thereafter directly patterning the masking layer 18 using known photolithography and etching techniques.
Next, as shown in FIG. 1B, one or more dry or wet etching processes is performed on the layers 16, 14 through the patterned mask layer 18 to form a plurality of trenches 13. In this example, the etching process stops on the substrate 12. This etching process results in the definition of a plurality of fin structures 16A that are each comprised of a portion of the layer of silicon 16.
Then, as shown in FIG. 1C, another etching process is performed to selectively remove the patterned portions of the layer 14 relative to the surrounding materials. FIG. 1D depicts the device 10 after another etching process has been performed to remove the patterned mask layer 18 selectively relative to the surrounding materials. Then, as shown in FIG. 1E, a layer of insulating material 20 is formed on the device 10 so as to overfill the spaces between the fins 16A. The layer of insulating material 20 may be comprised of a variety of different materials, such as, for example, silicon dioxide, etc. Next, although not depicted in the drawings, in some cases, a chemical mechanical polishing (CMP) process may be performed to planarize the upper surface of the layer of insulating material 20 using the fins 16A as a polish-stop layer. FIG. 1F depicts the device 10 after an etching process was performed on the layer of insulating material 20 to reduce its thickness and thereby result in the layer of insulating material 20 having a recessed upper surface 20R. The recessed surface 20R of the layer of insulating material 20 defines the final fin height for fins 16A and isolates the device 10 from the substrate 12.
Another illustrative prior art process flow that is typically performed to form FinFET devices involves forming a plurality of trenches in the substrate to define the areas where STI regions will be formed and to define the initial structure of the fins. In some cases, the trenches are desirably designed with the same pitch (for better resolution during lithography) and they are formed to the same depth and width (for processing simplicity), wherein the depth of the trenches is sufficient for the needed fin height and deep enough to allow formation of an effective STI region. After the trenches are formed, a layer of insulating material, such as silicon dioxide, is formed so as to overfill the trenches. Thereafter, a chemical mechanical polishing (CMP) process is performed to planarize the upper surface of the insulating material with the top of the fins (or the top of a patterned hard mask). Thereafter, an etch-back process is performed to recess the layer of insulating material between the fins and thereby expose the upper portions of the fins, which corresponds to the final fin height of the fins.
Unfortunately, such a prior art process flow is not without drawbacks. First, the formation of the silicon/germanium materials by performing an epitaxial growth process is a costly and time-consuming process. Moreover, the formation of silicon/germanium materials on silicon can lead to undesirable defects in what will become the channel region of the FinFET device.
Device manufacturers are under constant pressure to produce integrated circuit products with increased performance and lower production costs relative to previous device generations. Thus, device designers spend a great amount of time and effort to maximize device performance while seeking ways to reduce manufacturing cost and improve manufacturing reliability. As it relates to 3D devices, device designers have spent many years and employed a variety of techniques in an effort to improve the performance capability and reliability of such devices.
The present disclosure is directed to various methods of forming a dielectrically isolated FinFET semiconductor device using a novel etching process to form the fins for the device and to isolate the fins from the substrate and from one another, wherein the etch rate of the etching process is modified by inclusion of dopant materials.